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CY62127BV MoBL(R)
1M (64K x 16) Static RAM
Features
* High Speed: 55 ns and 70 ns * Wide voltage range: 2.7V-3.6V * Low active power -- 54 mW (max.) (15 mA) * Low standby power (70 ns) -- 54 W (max.) (15 A) * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Package available in a 44-pin TSOP Type II (forward pinout) and a 48-ball fBGA package significantly reduces power consumption when addresses are not toggling, or when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62127BV MoBL(R) MoBL(R) is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array 2048 X 512
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE CE BHE BLE
A11
A13
A12
A14
Power -Down Circuit
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05155 Rev. *B
*
3901 North First Street
A15
*
San Jose
*
CA 95134 * 408-943-2600 Revised August 27, 2002
CY62127BV MoBL(R)
Pin Configurations[2]
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 FBGA (Top View) 4 5 3 A0 A3 A5 NC A1 A4 A6 A7 NC A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 TSOP II (Forward) Top View A B C D E F G H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC
I/O12 DNU I/O13 NC A8 A14 A12 A9
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ................. -0.5V to 4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[3].................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial) VCC Range (V) Product CY62127BV MoBL(R) VCC(min.) 2.7 VCC(typ.)[4] 3.0 VCC(max.) 3.6 Speed (ns) 55 70 Operating, ICC (mA) f = fmax Max. 20 15 Standby, ISB2 (A) Typ.[4] 0.5 Max. 15
Notes: 2. NC pins are not connected to the die. 3. VIL(min.) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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CY62127BV MoBL(R)
Electrical Characteristics Over the Operating Range
CY62127BV MoBL(R)-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VI< VCC, Output Disabled f = fMAX = 1/tRC VCC = 3.6V IOUT = 0 mA CMOS Levels Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V 2.0 -0.3 -1 -1 Min. 2.2 0.4 VCC + 0.3V 0.4 +1 +1 20 2.0 -0.3 -1 -1 Typ.[4] Max. 2.2 0.4 VCC + 0.3V 0.4 +1 +1 15 CY62127BV MoBL(R)-70 Min. Typ.[4] Max. Unit V V V V A A mA
ISB1
Max. VCC, CE VIH VIN VIH or VIN VIL, f = fMAX Max. VCC, CE VCC - 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f=0 0.5
2
2
mA
ISB2
15
0.5
15 A
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 9 9 Unit pF pF
Thermal Resistance
Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol JA JC BGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2
VCC Typ 10% GND Rise TIme: 1 V/ns
ALL INPUT PULSES
90% 90% 10% Fall Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Note: 5. Tested initially and after any design or process changes that may affect these parameters.
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CY62127BV MoBL(R)
Parameters R1 R2 RTH VTH Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC 3.0V 1.076 1.262 0.581 1.620 Unit K Ohms K Ohms K Ohms Volts Min. Typ.[4] Max. Unit 2.0 0.5 3.6 15 V A ns ns
Data Retention Characteristics (Over the Operating Range)
Conditions
Data Retention Waveform[7]
DATA RETENTION MODE VCC CE or
3.0 V
tCDR
VDR > 2.0 V
3.0 V
tR
BHE.BLE
Switching Characteristics Over the Operating Range
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[10] tHZBE Write Cycle[12] tWC tSCE Write Cycle Time CE LOW to Write End Read Cycle Time Address to Data Valid Description
[8]
55 ns Min. 55 55 10 55 25 5 20 10 20 0 55 55 5 20 55 45 70 60 5 0 10 5 10 Max. Min. 70
70 ns Max. Unit ns 70 70 35 25 25 70 70 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[9] Z[9] OE HIGH to High Z[9, 11] CE HIGH to High Z[9, 11] CE LOW to Power-Up CE HIGH to Power-Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z[9] BHE / BLE HIGH to High Z[9, 11]
Notes: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62127BV MoBL(R)
Switching Characteristics Over the Operating Range (continued)[8]
55 ns Parameter tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Description Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BHE / BLE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[9, 11]
70 ns Max. Min. 60 0 0 50 60 30 0 25 25 5 Max. Unit ns ns ns ns ns ns ns ns ns
Min. 45 0 0 40 45 25 0 5
WE HIGH to Low Z[9]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
CE tACE OE
tRC tPD tHZCE
BHE/BLE
ttLZOE LZOE
tDOE
tHZOE
tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05155 Rev. *B
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CY62127BV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[12, 16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)
[12, 16, 17]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied.
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CY62127BV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 18 tHZWE DATAIN VALID
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[17]
tWC
ADDRESS CE
tSCE tAW tHA tBW tSA
BHE/BLE
tPWE
WE
tSD
tHD
DATA I/O
NOTE 18
DATAIN VALID
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X L L L L L
X X H H H H H
X X L L L H H
X H L H L L H
X H L L H L L
High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z
Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled
Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Page 7 of 11
Document #: 38-05155 Rev. *B
CY62127BV MoBL(R)
Truth Table (continued)
CE WE OE BHE BLE Inputs/Outputs Mode Power
L L L L
H L L L
H X X X
L L H L
H L L H
High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7) Data In (I/O8-I/O15)
Output Disabled Write Write Lower Byte Only Write Upper Byte Only
Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 70 Ordering Code CY62127BVLL-55ZI CY62127BVLL-70ZI CY62127BVLL-70BAI CY62127BVLL-70BVI BA48A BV48A 48-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Package Name Z44 44-lead TSOP II Package Type Operating Range Industrial
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51 -850 96-* E
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CY62127BV MoBL(R)
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-A
Document #: 38-05155 Rev. *B
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CY62127BV MoBL(R)
Package Diagrams (continued)
.
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05155 Rev. *B
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62127BV MoBL(R)
Document Title: CY62127BV MoBL(R) 1M (64K x 16) Static RAM Document Number: 38-05155 REV. ** *A *B ECN NO. 109899 113307 116362 Issue Date 10/02/01 03/01/02 09/04/02 Orig. of Change SZV MGN GBI Description of Change Change from Spec number: 38-01018 to 38-05155 Format standardization & update ordering information Add footnote 1 and BV Package.
Document #: 38-05155 Rev. *B
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